The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a chip, as well as methods of fabricating such chip structures.
A wafer may be processed by front-end-of-line processing to fabricate a plurality of substantially identical chips. Among other factors, the number of chips yielded from the wafer is a function of the individual chip size, as well as the wafer size. Each chip or die includes integrated circuits formed by the front-end-of-line processing, a local interconnect level formed by middle-end-of-line processing, and stacked metallization levels of an interconnect structure formed by back-end-of line processing. Dicing channels are present between the chips and are used during a dicing process to singulate the chips. The dicing process may induce stress into the chips, which may initiate stress cracks that can propagate into the active circuit area and lead to chip failures. After singulation from the wafer, chips may be packaged and mounted on a substrate, such as a circuit board or a laminate.
Improved structures and fabrication methods are needed that address crack formation and propagation.